Computer organization and architecture : designing for performance

Addresses fundamental principles in computer organization and architecture and the critical role of performance in driving computer design, covering superscalar design, IA-64 design features, and parallel processor organization trends. Offers numerous ongoing examples, especially of Pentium, plus de

Author Notes

WILLIAM STALLINGS has made a unique contribution to understanding the broad sweep of technical developments in computer networking and computer architecture. He has authored 17 titles, plus revised editions, for a total of 37 books on various aspects of these subjects. He has three times received the award for best Computer Science Textbook of the Year from the Text and Academic Authors Association (Computer Organization and Architecture, Prentice Hall, 1996; Data and Computer Communications, Prentice Hall, 1997; Operating Systems, Prentice Hall, 1998).
In over 20 years in the field, Dr. Stallings has been a technical contributor, technical manager and an executive with several high-technology firms. Currently he is an independent consultant whose clients have included computer and networking manufacturers and customers, software development firms and leading-edge government research institutions. Dr. Stallings is a frequent lecturer and a regular contributor to technical journals and trade publications.
Dr. Stallings holds a Ph.D. from MIT in computer science and a B.S. from Notre Dame in electrical engineering.

Web Site	p. vi
Preface	p. ix
Part I Overview	p. 1
Chapter 1 Introduction	p. 3
1.1 Organization and Architecture	p. 5
1.2 Structure and Function	p. 6
1.3 Outline of the Book	p. 12
1.4 Internet and Web Resources	p. 15
Chapter 2 Computer Evolution and Performance	p. 17
2.1 A Brief History of Computers	p. 19
2.2 Designing for Performance	p. 39
2.3 Pentium and PowerPC Evolution	p. 43
2.4 Recommended Reading and Web Sites	p. 46
2.5 Problems	p. 47
Part II The Computer System	p. 49
Chapter 3 System Buses	p. 51
3.1 Computer Components	p. 53
3.2 Computer Function	p. 56
3.3 Interconnection Structures	p. 69
3.4 Bus Interconnection	p. 71
3.5 PCI	p. 80
3.6 Recommended Reading and Web Sites	p. 89
3.7 Problems	p. 90
Appendix 3A Timing Diagrams	p. 92
Chapter 4 Internal Memory	p. 95
4.1 Computer Memory System Overview	p. 97
4.2 Semiconductor Main Memory	p. 103
4.3 Cache Memory	p. 117
4.4 Pentium II and PowerPC Cache Organizations	p. 132
4.5 Advanced DRAM Organization	p. 137
4.6 Recommended Reading and Web Sites	p. 142
4.7 Problems	p. 143
Appendix 4A Performance Characteristics of Two-Level Memories	p. 145
Chapter 5 External Memory	p. 153
5.1 Magnetic Disk	p. 155
5.2 RAID	p. 163
5.3 Optical Memory	p. 172
5.4 Magnetic Tape	p. 177
5.5 Recommended Reading and Web Sites	p. 178
5.6 Problems	p. 179
Chapter 6 Input/Output	p. 181
6.1 External Devices	p. 184
6.2 I/O Modules	p. 188
6.3 Programmed I/O	p. 191
6.4 Interrupt-Driven I/O	p. 195
6.5 Direct Memory Access	p. 203
6.6 I/O Channels and Processors	p. 207
6.7 The External Interface: SCSI and FireWire	p. 209
6.8 Recommended Reading and Web Sites	p. 223
6.9 Problems	p. 224
Chapter 7 Operating System Support	p. 227
7.1 Operating System Overview	p. 229
7.2 Scheduling	p. 241
7.3 Memory Management	p. 247
7.4 Pentium II and PowerPC Memory Management	p. 259
7.5 Recommended Reading and Web Sites	p. 268
7.6 Problems	p. 269
Part III The Central Processing Unit	p. 271
Chapter 8 Computer Arithmetic	p. 273
8.1 The Arithmetic and Logic Unit (ALU)	p. 275
8.2 Integer Representation	p. 276
8.3 Integer Arithmetic	p. 282
8.4 Floating-Point Representation	p. 298
8.5 Floating-Point Arithmetic	p. 305
8.6 Recommended Reading and Web Sites	p. 314
8.7 Problems	p. 315
Appendix 8A Number Systems	p. 317
Chapter 9 Instruction Sets: Characteristics and Functions	p. 323
9.1 Machine Instruction Characteristics	p. 325
9.2 Types of Operands	p. 331
9.3 Pentium II and PowerPC Data Types	p. 333
9.4 Types of Operations	p. 336
9.5 Pentium II and PowerPC Operation Types	p. 349
9.6 Assembly Language	p. 358
9.7 Recommended Reading	p. 360
9.8 Problems	p. 360
Appendix 9A Stacks	p. 364
Appendix 9B Little-, Big-, and Bi-Endian	p. 368
Chapter 10 Instruction Sets: Addressing Modes and Formats	p. 373
10.1 Addressing	p. 375
10.2 Pentium and PowerPC Addressing Modes	p. 382
10.3 Instruction Formats	p. 388
10.4 Pentium and PowerPC Instruction Formats	p. 397
10.5 Recommended Reading	p. 402
10.6 Problems	p. 402
Chapter 11 CPU Structure and Function	p. 405
11.1 Processor Organization	p. 407
11.2 Register Organization	p. 409
11.3 The Instruction Cycle	p. 414
11.4 Instruction Pipelining	p. 419
11.5 The Pentium Processor	p. 434
11.6 The PowerPC Processor	p. 443
11.7 Recommended Reading	p. 450
11.8 Problems	p. 451
Chapter 12 Reduced Instruction Set Computers	p. 455
12.1 Instruction Execution Characteristics	p. 458
12.2 The Use of a Large Register File	p. 462
12.3 Compiler-Based Register Optimization	p. 467
12.4 Reduced Instruction Set Architecture	p. 469
12.5 RISC Pipelining	p. 476
12.6 MIPS R4000	p. 480
12.7 SPARC	p. 488
12.8 The RISC versus CISC Controversy	p. 494
12.9 Recommended Reading	p. 495
12.10 Problems	p. 496
Chapter 13 Instruction-Level Parallelism and Superscalar Processors	p. 499
13.1 Overview	p. 501
13.2 Design Issues	p. 506
13.3 Pentium II	p. 515
13.4 PowerPC	p. 521
13.5 MIPS R10000	p. 529
13.6 UltraSPARC-II	p. 531
13.7 IA-64/Merced	p. 534
13.8 Recommended Reading	p. 545
13.9 Problems	p. 546
Part IV The Control Unit	p. 551
Chapter 14 Control Unit Operation	p. 553
14.1 Micro-operations	p. 555
14.2 Control of the Processor	p. 561
14.3 Hardwired Implementation	p. 573
14.4 Recommended Reading	p. 575
14.5 Problems	p. 576
Chapter 15 Microprogrammed Control	p. 577
15.1 Basic Concepts	p. 579
15.2 Microinstruction Sequencing	p. 588
15.3 Microinstruction Execution	p. 593
15.4 TI 8800	p. 605
15.5 Applications of Microprogramming	p. 615
15.6 Recommended Reading	p. 616
15.7 Problems	p. 617
Part V Parallel Organization	p. 619
Chapter 16 Parallel Processing	p. 621
16.1 Multiple Processor Organizations	p. 623
16.2 Symmetric Multiprocessors	p. 625
16.3 Cache Coherence and the MESI Protocol	p. 635
16.4 Clusters	p. 642
16.5 Nonuniform Memory Access	p. 646
16.6 Vector Computation	p. 650
16.7 Recommended Reading	p. 663
16.8 Problems	p. 664
Appendix A Digital Logic	p. 669
A.1 Boolean Algebra	p. 670
A.2 Gates	p. 672
A.3 Combinational Circuits	p. 675
A.4 Sequential Circuits	p. 696
A.5 Problems	p. 707
Appendix B Projects for Teaching Computer Organization and Architecture	p. 709
B.1 Research Projects	p. 710
B.2 Simulation Projects	p. 710
B.3 Reading/Report Assignments	p. 712
Glossary	p. 713
References	p. 725
Index	p. 739

Available:*

Bound With These Titles

On Order

Summary

Summary

Author Notes

Table of Contents