High speed digital system design : a handbook of interconnect theory and design practices

A cutting-edge guide to the theory and practice of high-speed digital system design

An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today's microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided.
Coverage includes:
* A thorough introduction to the digital aspects of basic transmission line theory
* Crosstalk and nonideal transmission line effects on signal quality and timings
* The impact of packages, vias, and connectors on signal integrity
* The effects of nonideal return current paths, high frequency power delivery, and simultaneous switching noise
* Explanations of how driving circuit characteristics affect the quality of the digital signal
* Digital timing analysis at the system level that incorporates high-speed signaling effects into timing budgets
* Methodologies for designing high-speed buses and handling the very large number of variables that affect interconnect performance
* Radiated emission problems and how to minimize system noise
* The practical aspects of making measurements in high-speed digital systems

Author Notes

Stephen H. Hall is a Senior Design Engineer at Intel Corporation, Portland, Oregon
Garrett W. Hall is a Silicon Systems Engineer at Intel Corporation
James A. McCall is a Senior Design Engineer at Intel Corporation

Reviews (1)

Choice Review

Hall, Hall, and McCall, all from Intel Corporation, offer an excellent guidebook for interconnect design. They bring a wealth of practical experience to this book, and their writing is exceptionally clear and intuitive. The book is intentionally brief in the area of theory, and it does not contain many complex equations; chapter introductions are outstanding and provide insight. The book easily transitions from detailed component-level material (e.g., choosing a decoupling capacitor in a power delivery system) to broader design concepts (e.g., enclosure considerations and bus topologies). The 11 chapters and six appendixes span topics relating to printed circuit board design, connectors, timing analysis, overall design optimization, and even high-speed measurement techniques. Appendixes cover topics from very basic (e.g., definition of the decibel) to applied (e.g., FCC emission limits). Since this book covers material not typically part of college courses, it would not be considered a textbook. Instead, this very valuable work is highly recommended for design engineers and recent graduates struggling to transition from theory to real-world design. Professional level. M. S. Roden; California State University, Los Angeles

Preface	p. xi
1. The Importance of Interconnect Design	p. 1
1.1 The Basics	p. 2
1.2 The Past and the Future	p. 4
2. Ideal Transmission Line Fundamentals	p. 7
2.1 Transmission Line Structures on a PCB or MCM	p. 7
2.2 Wave Propagation	p. 8
2.3 Transmission Line Parameters	p. 9
2.3.1 Characteristic Impedance	p. 11
2.3.2 Propagation Velocity, Time, and Distance	p. 14
2.3.3 Equivalent Circuit Models for SPICE Simulation	p. 15
2.4 Launching Initial Wave and Transmission Line Reflections	p. 18
2.4.1 Initial Wave	p. 18
2.4.2 Multiple Reflections	p. 19
2.4.3 Effect of Rise Time on Reflections	p. 26
2.4.4 Reflections From Reactive Loads	p. 28
2.4.5 Termination Schemes to Eliminate Reflections	p. 32
2.5 Additional Examples	p. 36
2.5.1 Problem	p. 36
2.5.2 Goals	p. 36
2.5.3 Calculating the Cross-Sectional Geometry of the PCB	p. 37
2.5.4 Calculating the Propagation Delay	p. 38
2.5.5 Determining the Wave Shape Seen at the Receiver	p. 39
2.5.6 Creating an Equivalent Circuit	p. 40
3. Crosstalk	p. 42
3.1 Mutual Inductance and Mutual Capacitance	p. 42
3.2 Inductance and Capacitance Matrix	p. 43
3.3 Field Simulators	p. 45
3.4 Crosstalk-Induced Noise	p. 45
3.5 Simulating Crosstalk Using Equivalent Circuit Models	p. 51
3.6 Crosstalk-Induced Flight Time and Signal Integrity Variations	p. 52
3.6.1 Effect of Switching Patterns on Transmission Line Performance	p. 53
3.6.2 Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model	p. 59
3.7 Crosstalk Trends	p. 62
3.8 Termination of Odd- and Even-Mode Transmission Line Pairs	p. 65
3.8.1 Pi Termination Network	p. 65
3.8.2 T Termination Network	p. 66
3.9 Minimization of Crosstalk	p. 67
3.10 Additional Examples	p. 68
3.10.1 Problem	p. 69
3.10.2 Goals	p. 70
3.10.3 Determining the Maximum Crosstalk-Induced Impedance and Velocity Swing	p. 70
3.10.4 Determining if Crosstalk Will Induce False Triggers	p. 72
4. Nonideal Interconnect Issues	p. 74
4.1 Transmission Line Losses	p. 74
4.1.1 Conductor DC Losses	p. 75
4.1.2 Dielectric DC Losses	p. 75
4.1.3 Skin Effect	p. 76
4.1.4 Frequency-Dependent Dielectric Losses	p. 87
4.2 Variations in the Dielectric Constant	p. 91
4.3 Serpentine Traces	p. 92
4.4 Intersymbol Interference	p. 95
4.5 Effects of 90[deg] Bends	p. 97
4.6 Effect of Topology	p. 99
5. Connectors, Packages, and Vias	p. 102
5.1 Vias	p. 102
5.2 Connectors	p. 104
5.2.1 Series Inductance	p. 104
5.2.2 Shunt Capacitance	p. 105
5.2.3 Connector Crosstalk	p. 105
5.2.4 Effects of Inductively Coupled Connector Pin Fields	p. 106
5.2.5 EMI	p. 109
5.2.6 Connector Design Guidelines	p. 110
5.3 Chip Packages	p. 112
5.3.1 Common Types of Packages	p. 113
5.3.2 Creating a Package Model	p. 117
5.3.3 Effects of a Package	p. 121
5.3.4 Optimal Pin-Outs	p. 127
6. Nonideal Return Paths, Simultaneous Switching Noise, and Power Delivery	p. 129
6.1 Nonideal Current Return Paths	p. 129
6.1.1 Path of Least Inductance	p. 129
6.1.2 Signals Traversing a Ground Gap	p. 130
6.1.3 Signals That Change Reference Planes	p. 134
6.1.4 Signals Referenced to a Power or a Ground Plane	p. 135
6.1.5 Other Nonideal Return Path Scenarios	p. 140
6.1.6 Differential Signals	p. 140
6.2 Local Power Delivery Networks	p. 141
6.2.1 Determining the Local Decoupling Requirements for High-Speed I/O	p. 144
6.2.2 System-Level Power Delivery	p. 147
6.2.3 Choosing a Decoupling Capacitor	p. 149
6.2.4 Frequency Response of a Power Delivery System	p. 150
6.3 SSO/SSN	p. 151
6.3.1 Minimizing SSN	p. 154
7. Buffer Modeling	p. 156
7.1 Types of Models	p. 157
7.2 Basic CMOS Output Buffer	p. 157
7.2.1 Basic Operation	p. 157
7.2.2 Linear Modeling of the CMOS Buffer	p. 164
7.2.3 Behavioral Modeling of the Basic CMOS Buffer	p. 172
7.3 Output Buffers That Operate in the Saturation Region	p. 175
7.4 Conclusions	p. 177
8. Digital Timing Analysis	p. 178
8.1 Common-Clock Timing	p. 178
8.1.1 Common-Clock Timing Equations	p. 180
8.2 Source Synchronous Timing	p. 183
8.2.1 Source Synchronous Timing Equations	p. 186
8.2.2 Deriving Source Synchronous Timing Equations from an Eye Diagram	p. 189
8.2.3 Alternative Source Synchronous Schemes	p. 191
8.3 Alternative Bus Signaling Techniques	p. 192
8.3.1 Incident Clocking	p. 192
8.3.2 Embedded Clock	p. 192
9. Design Methodologies	p. 194
9.1 Timings	p. 195
9.1.1 Worst-Case Timing Spreadsheet	p. 196
9.1.2 Statistical Spreadsheets	p. 198
9.2 Timing Metrics, Signal Quality Metrics, and Test Loads	p. 200
9.2.1 Voltage Reference Uncertainty	p. 200
9.2.2 Simulation Reference Loads	p. 202
9.2.3 Flight Time	p. 206
9.2.4 Flight-Time Skew	p. 207
9.2.5 Signal Integrity	p. 209
9.3 Design Optimization	p. 210
9.3.1 Paper Analysis	p. 211
9.3.2 Routing Study	p. 212
9.4 Sensitivity Analysis	p. 215
9.4.1 Initial Trend and Significance Analysis	p. 215
9.4.2 Ordered Parameter Sweeps	p. 221
9.4.3 Phase 1 Solution Space	p. 224
9.4.4 Phase 2 Solution Space	p. 225
9.4.5 Phase 3 Solution Space	p. 228
9.5 Design Guidelines	p. 229
9.6 Extraction	p. 230
9.7 General Rules of Thumb to Follow When Designing a System	p. 230
10. Radiated Emissions Compliance and System Noise Minimization	p. 232
10.1 FCC Radiated Emission Specifications	p. 233
10.2 Physical Mechanisms of Radiation	p. 233
10.2.1 Differential-Mode Radiation	p. 234
10.2.2 Common-Mode Radiation	p. 241
10.2.3 Wave Impedance	p. 245
10.3 Decoupling and Choking	p. 246
10.3.1 High-Frequency Decoupling at the System Level	p. 248
10.3.2 Choking Cables and Localized Power and Ground Planes	p. 253
10.3.3 Low-Frequency Decoupling and Ground Isolation	p. 261
10.4 Additional PCB Design Criteria, Package Considerations, and Pin-Outs	p. 263
10.4.1 Placement of High-Speed Components and Traces	p. 263
10.4.2 Crosstalk	p. 263
10.4.3 Pin Assignments and Package Choice	p. 264
10.5 Enclosure (Chassis) Considerations	p. 265
10.5.1 Shielding Basics	p. 265
10.5.2 Apertures	p. 267
10.5.3 Resonances	p. 272
10.6 Spread Spectrum Clocking	p. 273
11. High-Speed Measurement Techniques	p. 276
11.1 Digital Oscilloscopes	p. 276
11.1.1 Bandwidth	p. 277
11.1.2 Sampling	p. 278
11.1.3 Other Effects	p. 281
11.1.4 Statistics	p. 283
11.2 Time-Domain Reflectometry	p. 283
11.2.1 TDR Theory	p. 284
11.2.2 Measurement Factors	p. 287
11.3 TDR Accuracy	p. 289
11.3.1 Launch Parasitics	p. 290
11.3.2 Probe Types	p. 292
11.3.3 Reflections	p. 293
11.3.4 Interface Transmission Loss	p. 293
11.3.5 Cable Loss	p. 294
11.3.6 Amplitude Offset Error	p. 294
11.4 Impedance Measurement	p. 295
11.4.1 Accurate Characterization of Impedance	p. 295
11.4.2 Measurement Region in TDR Impedance Profile	p. 297
11.5 Odd- and Even-Mode Impedance	p. 299
11.6 Crosstalk Noise	p. 299
11.7 Propagation Velocity	p. 300
11.7.1 Length Difference Method	p. 301
11.7.2 Y-Intercept Method	p. 301
11.7.3 TDT Method	p. 302
11.8 Vector Network Analyzer	p. 303
11.8.1 Introduction to S Parameters	p. 304
11.8.2 Equipment	p. 305
11.8.3 One-Port Measurements (Z[subscript o],L,C)	p. 305
11.8.4 Two-Port Measurements (T[subscript d], Attenuation, Crosstalk)	p. 310
11.8.5 Calibration	p. 314
11.8.6 Calibration for One-Port Measurements	p. 315
11.8.7 Calibration for Two-Port Measurements	p. 316
11.8.8 Calibration Verification	p. 316
Appendix A Alternative Characteristic Impedance Formulas	p. 318
A.1 Microstrip	p. 318
A.2 Symmetric Stripline	p. 319
A.3 Offset Stripline	p. 319
Appendix B GTL Current-Mode Analysis	p. 321
B.1 Basic GTL Operation	p. 321
B.2 GTL Transitions When a Middle Agent Is Driving	p. 323
B.3 GTL Transitions When an End Agent With a Termination Is Driving	p. 325
B.4 Transitions When There is a Pull-Up at the Middle Agent	p. 327
Appendix C Frequency-Domain Components in a Digital Signal	p. 329
Appendix D Useful S-Parameter Conversions	p. 332
D.1 ABCD, Z, and Y Parameters	p. 332
D.2 Normalizing the S Matrix to a Different Characteristic Impedance	p. 335
D.3 Derivation of the Formulas Used to Extract the Mutual Inductance and Capacitance from a Short Structure Using S[subscript 21] Measurements	p. 336
D.4 Derivation of the Formula to Extract Skin Effect Resistance from a Transmission Line	p. 337
Appendix E Definition of the Decibel	p. 338
Appendix F FCC Emission Limits	p. 340
Bibliography	p. 342
Index	p. 345

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