Başlık:
Digital design
Yazar:
Mano, M. Morris, 1927-
ISBN:
9780130621214
Ek Yazar:
Edition:
3rd ed.
Yayım Bilgisi:
Upper Saddle River, NJ : Prentice Hall, c2002.
Fiziksel Tanım:
xii, 516 p. : ill. ; 25 cm. + 1 computer optical disc.
General Note:
Accompanying computer optical disc produced by Synapticad, Blacksburg, VA. and includes examples from the 3rd ed. of Digital design.
Mevcut:*
Library | Materyal Türü | Barkod | Yer Numarası | Durum |
|---|---|---|---|---|
Searching... Pamukkale Merkez Kütüphanesi | Kitap | 0019636 | TK7888.4.M343 2002 2 KOPYA | Searching... Unknown |
Bound With These Titles
On Order
Özet
Özet
For sophomore courses on digital design in an Electrical Engineering, Computer Engineering, or Computer Science department. & Digital Design, fourth edition is a modern update of the classic authoritative text on digital design.& This book teaches the basic concepts of digital design in a clear, accessible manner. The book presents the basic tools for the design of digital circuits and provides procedures suitable for a variety of digital applications.
Table of Contents
| Preface | p. ix |
| 1 Binary Systems | p. 1 |
| 1-1 Digital Computers and Digital Systems | p. 1 |
| 1-2 Binary Numbers | p. 4 |
| 1-3 Number Base Conversions | p. 6 |
| 1-4 Octal and Hexadecimal Numbers | p. 9 |
| 1-5 Complements | p. 10 |
| 1-6 Signed Binary Numbers | p. 14 |
| 1-7 Binary Codes | p. 17 |
| 1-8 Binary Storage and Registers | p. 25 |
| 1-9 Binary Logic | p. 28 |
| References | p. 32 |
| Problems | p. 33 |
| 2 Boolean Algebra and Logic Gates | p. 36 |
| 2-1 Basic Definitions | p. 36 |
| 2-2 Axiomatic Definition of Boolean Algebra | p. 38 |
| 2-3 Basic Theorems and Properties of Boolean Algebra | p. 41 |
| 2-4 Boolean Functions | p. 45 |
| 2-5 Canonical and Standard Forms | p. 49 |
| 2-6 Other Logic Operations | p. 56 |
| 2-7 Digital Logic Gates | p. 58 |
| 2-8 Integrated Circuits | p. 62 |
| References | p. 69 |
| Problems | p. 69 |
| 3 Simplification of Boolean Functions | p. 72 |
| 3-1 The Map Method | p. 72 |
| 3-2 Two- and Three-Variable Maps | p. 73 |
| 3-3 Four-Variable Map | p. 78 |
| 3-4 Five-Variable Map | p. 82 |
| 3-5 Product of Sums Simplification | p. 84 |
| 3-6 NAND and NOR Implementation | p. 88 |
| 3-7 Other Two-Level Implementations | p. 94 |
| 3-8 Don't-Care Conditions | p. 98 |
| 3-9 The Tabulation Method | p. 101 |
| 3-10 Determination of Prime Implicants | p. 101 |
| 3-11 Selection of Prime Implicants | p. 106 |
| 3-12 Concluding Remarks | p. 108 |
| References | p. 110 |
| Problems | p. 111 |
| 4 Combinational Logic | p. 114 |
| 4-1 Introduction | p. 114 |
| 4-2 Design Procedure | p. 115 |
| 4-3 Adders | p. 116 |
| 4-4 Subtractors | p. 121 |
| 4-5 Code Conversion | p. 124 |
| 4-6 Analysis Procedure | p. 126 |
| 4-7 Multilevel NAND Circuits | p. 130 |
| 4-8 Multilevel NOR Circuits | p. 138 |
| 4-9 Exclusive-OR Functions | p. 142 |
| References | p. 148 |
| Problems | p. 149 |
| 5 MSI and PLD Components | p. 152 |
| 5-1 Introduction | p. 152 |
| 5-2 Binary Adder and Subtractor | p. 154 |
| 5-3 Decimal Adder | p. 160 |
| 5-4 Magnitude Comparator | p. 163 |
| 5-5 Decoders and Encoders | p. 166 |
| 5-6 Multiplexers | p. 173 |
| 5-7 Read-Only Memory (ROM) | p. 180 |
| 5-8 Programmable Logic Array (PLA) | p. 187 |
| 5-9 Programmable Array Logic (PAL) | p. 192 |
| References | p. 197 |
| Problems | p. 197 |
| 6 Synchronous Sequential Logic | p. 202 |
| 6-1 Introduction | p. 202 |
| 6-2 Flip-Flops | p. 204 |
| 6-3 Triggering of Flip-Flops | p. 210 |
| 6-4 Analysis of Clocked Sequential Circuits | p. 218 |
| 6-5 State Reduction and Assignment | p. 228 |
| 6-6 Flip-Flop Excitation Tables | p. 231 |
| 6-7 Design Procedure | p. 236 |
| 6-8 Design of Counters | p. 247 |
| References | p. 251 |
| Problems | p. 251 |
| 7 Registers, Counters, and the Memory Unit | p. 257 |
| 7-1 Introduction | p. 257 |
| 7-2 Registers | p. 258 |
| 7-3 Shift Registers | p. 264 |
| 7-4 Ripple Counters | p. 272 |
| 7-5 Synchronous Counters | p. 277 |
| 7-6 Timing Sequences | p. 285 |
| 7-7 Random-Access Memory (RAM) | p. 289 |
| 7-8 Memory Decoding | p. 293 |
| 7-9 Error-Correcting Codes | p. 299 |
| References | p. 302 |
| Problems | p. 303 |
| 8 Algorithmic State Machines (ASM) | p. 307 |
| 8-1 Introduction | p. 307 |
| 8-2 ASM Chart | p. 309 |
| 8-3 Timing Considerations | p. 312 |
| 8-4 Control Implementation | p. 317 |
| 8-5 Design with Multiplexers | p. 323 |
| 8-6 PLA Control | p. 330 |
| References | p. 336 |
| Problems | p. 337 |
| 9 Asynchronous Sequential Logic | p. 341 |
| 9-1 Introduction | p. 341 |
| 9-2 Analysis Procedure | p. 343 |
| 9-3 Circuits with Latches | p. 352 |
| 9-4 Design Procedure | p. 359 |
| 9-5 Reduction of State and Flow Tables | p. 366 |
| 9-6 Race-Free State Assignment | p. 374 |
| 9-7 Hazards | p. 379 |
| 9-8 Design Example | p. 385 |
| References | p. 391 |
| Problems | p. 392 |
| 10 Digital Integrated Circuits | p. 399 |
| 10-1 Introduction | p. 399 |
| 10-2 Special Characteristics | p. 401 |
| 10-3 Bipolar-Transistor Characteristics | p. 406 |
| 10-4 RTL and DTL Circuits | p. 409 |
| 10-5 Transistor-Transistor Logic (TTL) | p. 412 |
| 10-6 Emmitter-Coupled Logic (ECL) | p. 422 |
| 10-7 Metal-Oxide Semiconductor (MOS) | p. 424 |
| 10-8 Complementary MOS (CMOS) | p. 427 |
| 10-9 CMOS Transmission Gate Circuits | p. 430 |
| References | p. 433 |
| Problems | p. 434 |
| 11 Laboratory Experiments | p. 436 |
| 11-0 Introduction to Experiments | p. 436 |
| 11-1 Binary and Decimal Numbers | p. 441 |
| 11-2 Digital Logic Gates | p. 444 |
| 11-3 Simplification of Boolean Functions | p. 446 |
| 11-4 Combinational Circuits | p. 447 |
| 11-5 Code Converters | p. 449 |
| 11-6 Design with Multiplexers | p. 451 |
| 11-7 Adders and Subtractors | p. 452 |
| 11-8 Flip-Flops | p. 455 |
| 11-9 Sequential Circuits | p. 458 |
| 11-10 Counters | p. 459 |
| 11-11 Shift Registers | p. 461 |
| 11-12 Serial Addition | p. 464 |
| 11-13 Memory Unit | p. 465 |
| 11-14 Lamp Handball | p. 467 |
| 11-15 Clock-Pulse Generator | p. 471 |
| 11-16 Parallel Adder | p. 473 |
| 11-17 Binary Multiplier | p. 475 |
| 11-18 Asynchronous Sequential Circuits | p. 477 |
| 12 Standard Graphic Symbols | p. 479 |
| 12-1 Rectangular-Shape Symbols | p. 479 |
| 12-2 Qualifying Symbols | p. 482 |
| 12-3 Dependency Notation | p. 484 |
| 12-4 Symbols for Combinational Elements | p. 486 |
| 12-5 Symbols for Flip-Flops | p. 489 |
| 12-6 Symbols for Registers | p. 491 |
| 12-7 Symbols for Counters | p. 494 |
| 12-8 Symbol for RAM | p. 496 |
| References | p. 497 |
| Problems | p. 497 |
| Appendix Answers to Selected Problems | p. 499 |
| Index | p. 512 |
Select a list
The following items were successfully added.
There was an error while adding the following items. Please try again.
One or more items could not be added because you are not logged in.
