The designer's guide to VHDL

Başlık:

Yazar:

Ashenden, Peter J.

ISBN:

9781558602700

Ek Yazar:

Ashenden, Peter J.

Yayım Bilgisi:

Fiziksel Tanım:

xxii, 688 s. : şkl. ; 24 cm.

Abstract:

The Designer's Guide to VHDL is both a comprehensive manual for the language and an authoritative reference on its use in hardware design at all levels, from the system level to the gate level. Using the IEEE standard for VHDL, the author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Requiring only a minimal background in programming, this is an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. The book is organized so that it can be either read cover-to-cover for a comprehensive tutorial or kept deskside as a reference to the language. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are four case studies, which bring together preceding material in the form of extended worked examples. All of the examples and case studies, complete with test drivers for running the VHDL code, are available via the World Wide Web. In addition, each chapter is followed by a set of related exercises.

Konu Terimleri:

VHDL (Bilgisayar donanımı açıklama dili)

VHDL (Computer hardware description language)

Elektronik dijital bilgisayarlar -- Bilgisayar simülasyonu.

Electronic digital computers -- Computer simulation.

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Library	Materyal Türü	Barkod	Yer Numarası	Durum
Searching... Pamukkale Merkez Kütüphanesi	Kitap	0096234	TK7888.3 .A863 1996	Searching... Unknown

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Özet

The Designer's Guide to VHDL is both a manual for the language and a reference on its use in hardware design at all levels, from system level down to gate level. Using the IEEE standard for VHDL, the author presents the description language and builds a modeling methodology based on successful software engineering techniques.

Paul MenchiniPaul Menchini

Foreword	p. vii
Foreword to the First Edition	p. ix
Preface	p. xix
1 Fundamental Concepts	p. 1
1.1 Modeling Digital Systems	p. 2
1.2 Domains and Levels of Modeling	p. 4
1.3 Modeling Languages	p. 7
1.4 VHDL Modeling Concepts	p. 8
Elements of Behavior	p. 9
Elements of Structure	p. 10
Mixed Structural and Behavioral Models	p. 12
Test Benches	p. 13
Analysis, Elaboration and Execution	p. 14
1.5 Learning a New Language: Lexical Elements and Syntax	p. 16
Lexical Elements	p. 17
Syntax Descriptions	p. 23
Exercises	p. 26
2 Scalar Data Types and Operations	p. 29
2.1 Constants and Variables	p. 30
Constant and Variable Declarations	p. 30
Variable Assignment	p. 32
2.2 Scalar Types	p. 32
Type Declarations	p. 33
Integer Types	p. 33
Floating-Point Types	p. 36
Physical Types	p. 37
Enumeration Types	p. 40
2.3 Type Classification	p. 46
Subtypes	p. 46
Type Qualification	p. 48
Type Conversion	p. 49
2.4 Attributes of Scalar Types	p. 49
2.5 Expressions and Operators	p. 52
Exercises	p. 54
3 Sequential Statements	p. 57
3.1 If Statements	p. 58
3.2 Case Statements	p. 61
3.3 Null Statements	p. 66
3.4 Loop Statements	p. 67
Exit Statements	p. 68
Next Statements	p. 71
While Loops	p. 72
For Loops	p. 74
Summary of Loop Statements	p. 76
3.5 Assertion and Report Statements	p. 77
Exercises	p. 83
4 Composite Data Types and Operations	p. 85
4.1 Arrays	p. 86
Multidimensional Arrays	p. 88
Array Aggregates	p. 89
Array Attributes	p. 92
4.2 Unconstrained Array Types	p. 94
Strings	p. 95
Bit Vectors	p. 95
Standard-Logic Arrays	p. 96
String and Bit-String Literals	p. 96
Unconstrained Array Ports	p. 97
4.3 Array Operations and Referencing	p. 98
Array Slices	p. 100
Array Type Conversions	p. 101
4.4 Records	p. 102
Record Aggregates	p. 104
Exercises	p. 105
5 Basic Modeling Constructs	p. 107
5.1 Entity Declarations	p. 108
5.2 Architecture Bodies	p. 110
Concurrent Statements	p. 111
Signal Declarations	p. 111
5.3 Behavioral Descriptions	p. 113
Signal Assignment	p. 113
Signal Attributes	p. 115
Wait Statements	p. 118
Delta Delays	p. 121
Transport and Inertial Delay Mechanisms	p. 124
Process Statements	p. 130
Concurrent Signal Assignment Statements	p. 131
Concurrent Assertion Statements	p. 138
Entities and Passive Processes	p. 139
5.4 Structural Descriptions	p. 140
Component Instantiation and Port Maps	p. 141
5.5 Design Processing	p. 149
Analysis	p. 149
Design Libraries, Library Clauses and Use Clauses	p. 151
Elaboration	p. 153
Execution	p. 156
Exercises	p. 157
6 Case Study: A Pipelined Multiplier Accumulator	p. 167
6.1 Algorithm Outline	p. 168
MAC Entity Declaration	p. 170
6.2 A Behavioral Model	p. 171
Testing the Behavioral Model	p. 176
6.3 A Register-Transfer-Level Model	p. 179
Modules in the Register-Transfer-Level Model	p. 181
The Register-Transfer-Level Architecture Body	p. 188
Testing the Register-Transfer-Level Model	p. 191
Exercises	p. 193
7 Subprograms	p. 195
7.1 Procedures	p. 196
Return Statement in a Procedure	p. 201
7.2 Procedure Parameters	p. 202
Signal Parameters	p. 206
Default Values	p. 209
Unconstrained Array Parameters	p. 210
Summary of Procedure Parameters	p. 212
7.3 Concurrent Procedure Call Statements	p. 213
7.4 Functions	p. 215
Functional Modeling	p. 218
Pure and Impure Functions	p. 218
The Function Now	p. 219
7.5 Overloading	p. 220
Overloading Operator Symbols	p. 222
7.6 Visibility of Declarations	p. 223
Exercises	p. 227
8 Packages and Use Clauses	p. 231
8.1 Package Declarations	p. 232
Subprograms in Package Declarations	p. 236
Constants in Package Declarations	p. 237
8.2 Package Bodies	p. 239
8.3 Use Clauses	p. 241
8.4 The Predefined Package Standard	p. 243
8.5 IEEE Standard Packages	p. 244
Std_Logic_1164 Multivalue Logic System	p. 245
Standard VHDL Synthesis Packages	p. 246
Standard VHDL Mathematical Packages	p. 250
Exercises	p. 255
9 Aliases	p. 257
9.1 Aliases for Data Objects	p. 258
9.2 Aliases for Non-Data Items	p. 261
Exercises	p. 264
10 Case Study: A Bit-Vector Arithmetic Package	p. 267
10.1 The Package Interface	p. 268
10.2 The Package Body	p. 271
10.3 An ALU Using the Arithmetic Package	p. 280
Exercises	p. 282
11 Resolved Signals	p. 285
11.1 Basic Resolved Signals	p. 286
Composite Resolved Subtypes	p. 290
Summary of Resolved Subtypes	p. 294
11.2 IEEE Std_Logic_1164 Resolved Subtypes	p. 294
11.3 Resolved Signals and Ports	p. 297
Resolved Ports	p. 298
Driving Value Attribute	p. 300
11.4 Resolved Signal Parameters	p. 300
Exercises	p. 302
12 Generic Constants	p. 309
12.1 Parameterizing Behavior	p. 310
12.2 Parameterizing Structure	p. 313
Exercises	p. 315
13 Components and Configurations	p. 317
13.1 Components	p. 318
Component Declarations	p. 318
Component Instantiation	p. 319
Packaging Components	p. 321
13.2 Configuring Component Instances	p. 322
Basic Configuration Declarations	p. 323
Configuring Multiple Levels of Hierarchy	p. 325
Direct Instantiation of Configured Entities	p. 328
Generic and Port Maps in Configurations	p. 329
Deferred Component Binding	p. 335
13.3 Configuration Specifications	p. 337
Incremental Binding	p. 338
Exercises	p. 344
14 Generate Statements	p. 349
14.1 Generating Iterative Structures	p. 350
14.2 Conditionally Generating Structures	p. 355
Recursive Structures	p. 359
14.3 Configuration of Generate Statements	p. 362
Exercises	p. 367
15 Case Study: The DLX Computer System	p. 373
15.1 Overview of the DLX CPU	p. 374
DLX Registers	p. 374
DLX Instruction Set	p. 375
DLX External Interface	p. 379
15.2 A Behavioral Model	p. 382
The DLX Types Package	p. 382
The DLX Entity Declaration	p. 383
The DLX Instruction Set Package	p. 384
The DLX Behavioral Architecture Body	p. 392
15.3 Testing the Behavioral Model	p. 407
The Test-Bench Clock Generator	p. 408
The Test-Bench Memory	p. 408
The Test-Bench Architecture Body and Configuration	p. 413
15.4 A Register-Transfer-Level Model	p. 416
The Arithmetic and Logic Unit	p. 417
The Registers	p. 421
The Register File	p. 425
The Multiplexer	p. 426
The Extenders	p. 427
The Architecture Body	p. 428
The Controller	p. 434
The Configuration Declaration	p. 450
15.5 Testing the Register-Transfer-Level Model	p. 452
Exercises	p. 456
16 Guards and Blocks	p. 459
16.1 Guarded Signals and Disconnection	p. 460
The Driving Attribute	p. 464
Guarded Ports	p. 465
Guarded Signal Parameters	p. 467
16.2 Blocks and Guarded Signal Assignment	p. 469
Explicit Guard Signals	p. 472
Disconnection Specifications	p. 474
16.3 Using Blocks for Structural Modularity	p. 475
Generics and Ports in Blocks	p. 478
Configuring Designs with Blocks	p. 479
Exercises	p. 482
17 Access Types and Abstract Data Types	p. 487
17.1 Access Types	p. 488
Access Type Declarations and Allocators	p. 488
Assignment and Equality of Access Values	p. 490
Access Types for Records and Arrays	p. 492
17.2 Linked Data Structures	p. 494
Deallocation and Storage Management	p. 498
17.3 Abstract Data Types Using Packages	p. 499
Container ADTs	p. 504
Exercises	p. 512
18 Files and Input/Output	p. 515
18.1 Files	p. 516
File Declarations	p. 516
Reading from Files	p. 517
Writing to Files	p. 520
Files Declared in Subprograms	p. 523
Explicit Open and Close Operations	p. 524
File Parameters in Subprograms	p. 527
Portability of Files	p. 529
18.2 The Package Textio	p. 529
Textio Read Operations	p. 531
Textio Write Operations	p. 541
Reading and Writing User-Defined Types	p. 543
Exercises	p. 544
19 Case Study: Queuing Networks	p. 549
19.1 Queuing Network Concepts	p. 550
19.2 Queuing Network Modules	p. 551
Random Number Generator	p. 551
A Package for Token and Arc Types	p. 555
The Token Source Module	p. 557
The Token Sink Module	p. 561
The Queue Module	p. 563
The Token Server Module	p. 569
The Fork Module	p. 571
The Join Module	p. 575
19.3 A Queuing Network for a Disk System	p. 578
Exercises	p. 584
20 Attributes and Groups	p. 585
20.1 Predefined Attributes	p. 586
Attributes of Scalar Types	p. 586
Attributes of Array Types and Objects	p. 587
Attributes of Signals	p. 587
Attributes of Named Items	p. 588
20.2 User-Defined Attributes	p. 595
Attribute Declarations	p. 596
Attribute Specifications	p. 596
The Attribute Foreign	p. 606
20.3 Groups	p. 608
Exercises	p. 611
21 Miscellaneous Topics	p. 615
21.1 Buffer and Linkage Ports	p. 616
21.2 Conversion Functions in Association Lists	p. 618
21.3 Postponed Processes	p. 623
21.4 Shared Variables	p. 626
Exercises	p. 636
A Synthesis	p. 639
A.1 Use of Data Types	p. 640
A.2 Interpretation of Standard Logic Values	p. 642
A.3 Modeling Combinatorial Logic	p. 643
A.4 Modeling Sequential Logic	p. 644
A.5 VHDL Modeling Restrictions	p. 650
B The Predefined Package Standard	p. 655
C IEEE Standard Packages	p. 659
C.1 Std_Logic_1164 Multivalue Logic System	p. 659
C.2 Standard 1076.3 VHDL Synthesis Packages	p. 662
C.3 Standard 1076.2 VHDL Mathematical Packages	p. 665
D Related Standards	p. 671
D.1 IEEE VHDL Standards	p. 671
D.2 Other Design Automation Standards	p. 677
E VHDL Syntax	p. 683
E.1 Design File	p. 685
E.2 Library Unit Declarations	p. 685
E.3 Declarations and Specifications	p. 686
E.4 Type Definitions	p. 689
E.5 Concurrent Statements	p. 690
E.6 Sequential Statements	p. 692
E.7 Interfaces and Associations	p. 693
E.8 Expressions	p. 694
F Differences among VHDL-87, VHDL-93 and VHDL-2001	p. 697
F.1 Lexical Differences	p. 697
F.2 Syntactic Differences	p. 698
F.3 Semantic Differences	p. 699
F.4 Differences in the Standard Environment	p. 700
F.5 VHDL-93 Facilities Not in VHDL-87	p. 701
F.6 VHDL-2001 Facilities Not in VHDL-87 or VHDL-93	p. 701
F.7 Features under Consideration for Removal	p. 701
G Answers to Exercises	p. 703
H Software Guide	p. 723
H.1 Software Overview	p. 723
H.2 Installation	p. 724
H.3 Example VHDL Code	p. 727
H.4 Exploration/VHDL Quick Start Guide	p. 728
References	p. 743
Index	p. 745

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